Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology
Wang, GL; Qin, CL; Yin, HX; Luo, J; Duan, NY; Yang, P; Gao, XY; Yang, T; Li, JF; Yan, J; Zhu, HL; Wang, WW; Chen, DP; Ye, TC; Zhao, C; Radamson, HH; Luo, J (reprint author), Chinese Acad Sci, Inst Microelect, Key Lab Microelect Devices & Integrated Technol, Beijing 100029, Peoples R China.
2016
发表期刊MICROELECTRONIC ENGINEERING
ISSN0167-9317
卷号163页码:49-54
文章类型期刊论文
摘要In this study, the process integration of SiGe selective epitaxy on source/drain regions, for 16/14 nm nodes FinFET with high-k & metal gate has been presented. Selectively grown Si1-xGex (0.35 <= x <= 0.40) with boron concentration of 1 x 10(20) cm(-3) was used to elevate the source/drain of the transistors. The epi-quality, layer profile and strain amount of the selectively grown SiGe layers were also investigated by means of various characterizations. A series of prebaking experiments were performed for temperatures ranging from 740 to 825 degrees C in order to in situ clean the Si fins prior to the epitaxy. The results showed that the thermal budget needs to be limited to 780-800 degrees C in order to avoid any damages to the shape of Si fins but to remove the native oxide effectively which is essential for high epitaxial quality. The Ge content in SiGe layers on Si fins was determined from the strain measured directly by reciprocal space mappings using synchrotron radiation. Atomic layer deposition technique was applied to fill the gate trench with W using WF6 and B2H6 precursors. By such an AID approach, decent growth rate, low resistivity and excellent gap filling capability of W in pretty high aspect-ratio gate trench was realized. The as-fabricated FinFETs demonstrated decent electrical characteristics. (C) 2016 Elsevier B.V. All rights reserved.
关键词Finfet Sige Selective Epitaxy Rpcvd High-k & Metal Gate
DOI10.1016/j.mee.2016.06.002
收录类别SCI
语种英语
WOS记录号WOS:000381837300008
引用统计
文献类型期刊论文
条目标识符http://ir.sinap.ac.cn/handle/331007/26635
专题中科院上海应用物理研究所2011-2018年
通讯作者Wang, GL; Luo, J (reprint author), Chinese Acad Sci, Inst Microelect, Key Lab Microelect Devices & Integrated Technol, Beijing 100029, Peoples R China.
推荐引用方式
GB/T 7714
Wang, GL,Qin, CL,Yin, HX,et al. Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology[J]. MICROELECTRONIC ENGINEERING,2016,163:49-54.
APA Wang, GL.,Qin, CL.,Yin, HX.,Luo, J.,Duan, NY.,...&Luo, J .(2016).Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology.MICROELECTRONIC ENGINEERING,163,49-54.
MLA Wang, GL,et al."Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology".MICROELECTRONIC ENGINEERING 163(2016):49-54.
条目包含的文件 下载所有文件
文件名称/大小 文献类型 版本类型 开放类型 使用许可
Study of SiGe select(1459KB)期刊论文作者接受稿开放获取CC BY-NC-SA浏览 下载
个性服务
推荐该条目
保存到收藏夹
查看访问统计
导出为Endnote文件
谷歌学术
谷歌学术中相似的文章
[Wang, GL]的文章
[Qin, CL]的文章
[Yin, HX]的文章
百度学术
百度学术中相似的文章
[Wang, GL]的文章
[Qin, CL]的文章
[Yin, HX]的文章
必应学术
必应学术中相似的文章
[Wang, GL]的文章
[Qin, CL]的文章
[Yin, HX]的文章
相关权益政策
暂无数据
收藏/分享
文件名: Study of SiGe selective epitaxial process integration with high-k and metal gate for 16_14 nm nodes FinFET technology.pdf
格式: Adobe PDF
所有评论 (0)
暂无评论
 

除非特别说明,本系统中所有内容都受版权保护,并保留所有权利。